Compiling for Increasing On-chip Parallelism

It becomes a trend that microprocessor companies are adding more and more parallelism on a chip to increase performance per chip. At the fine granularity level, vector instruction sets are added. While at the coarse granularity level, multiple cores are put on the same chip. This trend presents a challenge for application developers as well for compiler developers: how to exploit the power of these introduced parallelism? In this paper, we present a source-to-source compiler that automatically compiles programs written by ordinary users targeting the on-chip parallelism without users specifying parallelism directives. Initially developed for short vector processors, this compiler is extended to support a heterogeneous multi-core CELL processor. Besides parallelism, these processors also introduced various memory constraints such as data alignment and data movement that will affect an application’s performance. Thus we will discuss our compiler strategies for these issues as well. Keyword: On-chip Parallelism, Vectorization, Parallelization, Heterogeneous Multi-core, Memory Hierarchy Performance, Data Alignment, Data Movement, Vector Data Reuse